commit f2c7430f7c4f27a277227c08572b0249f82c0742
Author: Simon Kirby <sim@netnation.com>
Date:   Thu Mar 22 02:09:50 2012 -0700

    Ugly support for atmega48.

diff --git a/tgy.asm b/tgy.asm
index 51d4ee7..17c402d 100644
--- a/tgy.asm
+++ b/tgy.asm
@@ -50,7 +50,7 @@
 ;
 ;-- Device ----------------------------------------------------------------
 ;
-.include "m8def.inc"
+.include "m48def.inc"
 ;
 ; 8K Bytes of In-System Self-Programmable Flash
 ; 512 Bytes EEPROM
@@ -240,6 +240,78 @@
 ; ZH: Next PWM interrupt vector (high, stays at zero) -- used as "zero" register
 
 ;**** **** **** **** ****
+; Macros
+.MACRO outx
+.if @0 > 0x3f
+sts	@0, @1
+.else
+out	@0, @1
+.endif
+.ENDMACRO
+
+.MACRO inx
+.if @1 > 0x3f
+lds	@0, @1
+.else
+in	@0, @1
+.endif
+.ENDMACRO
+
+.MACRO cbix
+.if @0 > 0x31
+inx	@2, @0
+cbr	@2, @1
+outx	@0, @2
+.else
+cbi	@0, @1
+.endif
+.ENDMACRO
+
+.MACRO sbix
+.if @0 > 0x31
+inx	@2, @0
+sbr	@2, @1
+outx	@0, @2
+.else
+sbi	@0, @1
+.endif
+.ENDMACRO
+
+.if !defined(MCUCSR)
+.set MCUCSR = MCUSR
+.endif
+.if !defined(TCCR0B)
+.set TCCR0B = TCCR0
+.endif
+.if !defined(WDTCSR)
+.set WDTCSR = WDTCR
+.endif
+.if !defined(SPMCSR)
+.set SPMCSR = SPMCR
+.endif
+.if !defined(SELFPRGEN)
+.set SELFPRGEN = SPMEN
+.endif
+.if !defined(GICR)
+.set GICR = EIMSK
+.endif
+.if !defined(EICRA)
+.set EICRA = MCUCR
+.endif
+.if !defined(ADCSRB)
+.set ADCSRB = ADCSRA
+.endif
+.if !defined(TCCR2)
+.set TCCR2 = TCCR2B
+.endif
+.if !defined(TIFR2)
+.set TIFR2 = TIFR
+.set TIFR1 = TIFR
+.set TIFR0 = TIFR
+.set TIMSK1 = TIMSK
+.endif
+
+;**** **** **** **** ****
 ; RAM Definitions
 .dseg				; DATA segment
 .org SRAM_START
@@ -356,24 +428,26 @@ eeprom_defaults_w:
 
 reset:		clr	r0
 		out	SREG, r0		; Clear interrupts and flags
-
 	; Set up stack
-		ldi	ZH, high(RAMEND+1)
-		ldi	ZL, low(RAMEND+1)
+		ldi	ZH, high(RAMEND)
+		ldi	ZL, low(RAMEND)
 		out	SPH, ZH
 		out	SPL, ZL
+		ldi	XH, high(SRAM_START)
+		ldi	XL, low(SRAM_START)
 	; Clear RAM and all registers
+		st	Z, r0
 clear_loop:	st	-Z, r0
-		cpi	ZL, SRAM_START
-		cpc	ZH, r0
-		brne	clear_loop1
-		ldi	ZL, 30			; Start clearing registers
-clear_loop1:	cp	ZL, r0
-		cpc	ZH, r0
+		cp	ZH, XH
+		cpc	ZL, XL
+		brne	clear_loop
+		adiw	ZL, 0			; Set zero flag if ZL:ZH was zero
+		ldi	ZH, 0			; Start clearing registers at XH,
+		ldi	ZL, 30			; ending our loop by clearing X
 		brne	clear_loop		; Leaves with all registers (r0 through ZH) at 0
 
 	; Save original OSCCAL and reset cause
-		in	i_sreg, OSCCAL
+		inx	i_sreg, OSCCAL
 		sts	orig_osccal, i_sreg
 		in	i_sreg, MCUCSR
 		out	MCUCSR, r0
@@ -398,16 +472,16 @@ clear_loop1:	cp	ZL, r0
 
 	; Start timers except output PWM
 		ldi	temp1, T0CLK		; timer0: beep control, delays
-		out	TCCR0, temp1
+		out	TCCR0B, temp1
 		ldi	temp1, T1CLK		; timer1: commutation timing,
-		out	TCCR1B, temp1		; RC pulse measurement
-		out	TCCR2, ZH		; timer2: PWM, stopped
+		outx	TCCR1B, temp1		; RC pulse measurement
+		outx	TCCR2, ZH		; timer2: PWM, stopped
 
 	; Enable watchdog (WDTON may be set or unset)
 		ldi	temp1, (1<<WDCE)+(1<<WDE)
-		out	WDTCR, temp1
+		outx	WDTCSR, temp1
 		ldi	temp1, (1<<WDE)		; Fastest option: ~16.3ms timeout
-		out	WDTCR, temp1
+		outx	WDTCSR, temp1
 
 	; Read EEPROM block to RAM
 		rcall	wait120ms
@@ -523,7 +597,7 @@ pwm_on:
 		cpse	duty_h, ZH
 		ldi	ZL, pwm_off_high
 		mov	tcnt2h, duty_h
-		out	TCNT2, duty_l
+		outx	TCNT2, duty_l
 		reti
 
 pwm_off:
@@ -533,7 +607,7 @@ pwm_off:
 		mov	tcnt2h, off_duty_h	; 1 cycle
 		wdr				; 1 cycle
 		st	X, nfet_off		; 2 cycles (off at 7 cycles from entry)
-		out	TCNT2, off_duty_l	; 1 cycle
+		outx	TCNT2, off_duty_l	; 1 cycle
 		reti				; 4 cycles
 
 .if high(pwm_off)
@@ -576,8 +650,8 @@ rcp_int:
 		sbrs	i_sreg, ICES1		; evaluate edge of this interrupt
 		.else
 ;-----bko-----------------------------------------------------------------
-		in	i_temp1, TCNT1L		; get timer1 values
-		in	i_temp2, TCNT1H
+		inx	i_temp1, TCNT1L		; get timer1 values
+		inx	i_temp2, TCNT1H
 		sbis	PIND, rcp_in		; evaluate edge of this interrupt
 		.endif
 		rjmp	falling_edge		; bit is clear = falling edge
@@ -589,7 +663,7 @@ rising_edge:					; Flags not saved here!
 		sts	start_rcpuls_x, i_temp1
 		sbrc	i_temp2, 7
 		reti
-		in	i_temp2, TIFR
+		in	i_temp2, TIFR1
 		sbrs	i_temp2, TOV1
 		reti
 		in	i_sreg, SREG
@@ -608,7 +682,7 @@ falling_edge:
 		lds	XH, tcnt1x		; We borrow XH and ZH (normally 0)
 		sbrc	i_temp2, 7		; as additional registers and
 		rjmp	falling_edge1		; clear them before returning.
-		in	ZH, TIFR
+		in	ZH, TIFR1
 		sbrc	ZH, TOV1
 		inc	XH			; Compensate for postponed tcnt1x update
 falling_edge1:	lds	ZH, start_rcpuls_l
@@ -789,9 +863,9 @@ wait30ms:	ldi	temp2, 15
 beep_BpCn20:	ldi	temp3, CPU_MHZ
 beep_BpCn21:	out	TCNT0, ZH
 		ldi	temp1, (1<<TOV0)	; Clear TOV0 by setting it
-		out	TIFR, temp1
+		out	TIFR0, temp1
 		wdr
-beep_BpCn22:	in	temp1, TIFR
+beep_BpCn22:	in	temp1, TIFR0
 		sbrs	temp1, TOV0
 		rjmp	beep_BpCn22
 		dec	temp3
@@ -808,7 +882,7 @@ beep_BpCn22:	in	temp1, TIFR
 eeprom_read_block:				; When interrupts disabled
 eeprom_write_block:				; When interrupts enabled
 		lds	temp1, orig_osccal
-		out	OSCCAL, temp1
+		outx	OSCCAL, temp1
 		ldi	YL, low(eeprom_sig_l)
 		ldi	YH, high(eeprom_sig_l)
 		ldi	temp1, low(EEPROM_OFFSET)
@@ -816,8 +890,8 @@ eeprom_write_block:				; When interrupts enabled
 eeprom_rw1:	wdr
 		sbic	EECR, EEWE
 		rjmp	eeprom_rw1		; Loop while writing EEPROM
-		in	temp3, SPMCR
-		sbrc	temp3, SPMEN
+		in	temp3, SPMCSR
+		sbrc	temp3, SELFPRGEN
 		rjmp	eeprom_rw1		; Loop while flashing
 		cpi	YL, low(eeprom_end)
 		breq	eeprom_rw4
@@ -851,7 +925,7 @@ osccal_set:
 .else
 		ldi	temp1, 0x9f		; Almost 8MHz
 .endif
-		out	OSCCAL, temp1
+		outx	OSCCAL, temp1
 		ret
 ;-----bko-----------------------------------------------------------------
 ; Shift left temp7:temp6:temp5 temp1 times.
@@ -1163,7 +1237,7 @@ update_timing:
 	; interrupts have been enabled, because the AVR always executes one
 	; non-interrupt instruction between interrupts, and several other
 	; higher-priority interrupts may (have) come up. So, we must save
-	; tcnt1x and TIFR with interrupts disabled, then do a correction.
+	; tcnt1x and TIFR1 with interrupts disabled, then do a correction.
 		sbrc	temp2, 7		; If highest bit of TCNT1H is set,
 		rjmp	update_timing1		; we assume tcnt1x must be right.
 		sbrc	temp4, TOV1		; If TOV1 is/was pending,
@@ -1337,17 +1411,17 @@ calc_next_timing_and_wait:
 set_ocr1a:	adiw	YL, 7			; Compensate for timer increment during in-add-out
 		ldi	temp4, (1<<OCF1A)
 		cli
-		in	temp1, TCNT1L
-		in	temp2, TCNT1H
+		inx	temp1, TCNT1L
+		inx	temp2, TCNT1H
 		add	YL, temp1
 		adc	YH, temp2
-		out	OCR1AH, YH
-		out	OCR1AL, YL
-		out	TIFR, temp4		; Clear any pending OCF1A interrupt (7 cycles from TCNT1 read)
+		outx	OCR1AH, YH
+		outx	OCR1AL, YL
+		out	TIFR1, temp4		; Clear any pending OCF1A interrupt (7 cycles from TCNT1 read)
 		sts	ocr1ax, temp5
 		sbr	flags0, (1<<OCT1_PENDING)
 		lds	temp3, tcnt1x
-		in	temp4, TIFR
+		in	temp4, TIFR1
 		sei				; We could use reti here, but that's
 		ret				; 4 more cycles of interrupt latency
 ;-----bko-----------------------------------------------------------------
@@ -1458,9 +1532,9 @@ set_new_duty_zero:
 		rjmp	set_new_duty_set_off
 ;-----bko-----------------------------------------------------------------
 switch_power_off:
-		out	TCCR2, ZH		; Disable PWM
+		outx	TCCR2, ZH		; Disable PWM
 		ldi	temp1, (1<<TOV2)
-		out	TIFR, temp1		; Clear pending PWM interrupts
+		out	TIFR2, temp1		; Clear pending PWM interrupts
 		ldi	ZL, low(pwm_off)	; Set PWM interrupt vector
 		all_pFETs_off temp1
 		all_nFETs_off temp1
@@ -1474,8 +1548,8 @@ control_start:
 
 	; init registers and interrupts
 		ldi	temp1, (1<<TOIE1)+(1<<OCIE1A)+(1<<TOIE2)
-		out	TIFR, temp1		; clear TOIE1, OCIE1A & TOIE2
-		out	TIMSK, temp1		; enable TOIE1, OCIE1A & TOIE2 interrupts
+		out	TIFR1, temp1		; clear TOIE1, OCIE1A & TOIE2
+		outx	TIMSK1, temp1		; enable TOIE1, OCIE1A & TOIE2 interrupts
 
 		.if defined(HK_PROGRAM_CARD)
 	; This program card seems to send data at 1200 baud N81,
@@ -1608,7 +1682,7 @@ FETs_off_wt:	dec	temp1
 		rcall	com6com1		; Set comparator phase and nFET vector
 
 		ldi	temp1, T2CLK
-		out	TCCR2, temp1		; Enable PWM (ZL and XL have been set)
+		outx	TCCR2, temp1		; Enable PWM (ZL and XL have been set)
 
 ;-----bko-----------------------------------------------------------------
 ; **** running control loop ****
diff --git a/tgy.inc b/tgy.inc
index db5ddff..0c44379 100644
--- a/tgy.inc
+++ b/tgy.inc
@@ -32,18 +32,18 @@
 
 .MACRO rcp_int_enable
 	ldi	@0, (1<<INT0)	; enable ext0int
-	out	GICR, @0
+	outx	GICR, @0
 .ENDMACRO
 .MACRO rcp_int_disable
-	out	GICR, ZH	; disable ext0int
+	outx	GICR, ZH	; disable ext0int
 .ENDMACRO
 .MACRO rcp_int_rising_edge
 	ldi	@0, (1<<ISC01)+(1<<ISC00)
-	out	MCUCR, @0	; set next int0 to rising edge
+	outx	EICRA, @0	; set next int0 to rising edge
 .ENDMACRO
 .MACRO rcp_int_falling_edge
 	ldi	@0, (1<<ISC01)
-	out	MCUCR, @0	; set next int0 to falling edge
+	outx	EICRA, @0	; set next int0 to falling edge
 .ENDMACRO
 
 .MACRO ApFET_on
@@ -107,22 +107,22 @@
 .equ	DIR_PC		= 0
 
 .MACRO comp_init
-	in	@0, SFIOR
-	sbr	@0, (1<<ACME)	; set Analog Comparator Multiplexer Enable
-	out	SFIOR, @0
+	inx	@0, ADCSRB
+	sbr	@0, (1<<ACME)		; set Analog Comparator Multiplexer Enable
+	outx	ADCSRB, @0
 .ENDMACRO
 .MACRO set_comp_phase_a
-	ldi	@0, mux_a	; set comparator multiplexer to phase A
-	out	ADMUX, @0
-	cbi	ADCSRA, ADEN	; disable ADC
+	ldi	@0, mux_a		; set comparator multiplexer to phase A
+	outx	ADMUX, @0
+	cbix	ADCSRB, ADEN, @0	; disable ADC
 .ENDMACRO
 .MACRO set_comp_phase_b
-	ldi	@0, mux_b	; set comparator multiplexer to phase B
-	out	ADMUX, @0
-	cbi	ADCSRA, ADEN	; disable ADC
+	ldi	@0, mux_b		; set comparator multiplexer to phase B
+	outx	ADMUX, @0
+	cbix	ADCSRB, ADEN, @0	; disable ADC
 .ENDMACRO
 .MACRO set_comp_phase_c	
-	sbi	ADCSRA, ADEN	; enable ADC and comparator to phase C (AIN1)
+	sbix	ADCSRB, ADEN, @0	; enable ADC and comparator to phase C (AIN1)
 .ENDMACRO